c - Is it possible to use memory barriers only on the storing side -

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First of all, some references: I am working with the pre-C11, inline-ASM-based nuclear model, But I am happy to ignore the C aspect (and any compiler blocking issues that I can deal with separately) and only consider it as an asm / cpu-architecture question.

Suppose I have a code that looks like: 

  different store barrier store flag blocks   
 I  flag  from another CPU core and concluded that  different stores  were already made and visible, it is possible to do this  without any kind of memory barrier instructions loading side < / Em>? Obviously this is possible at least on some CPU architectures, for example x86 where there is no need for a clear memory hurdle either on the core or on the core. But what about general? Is it widely widespread by the CPU arc, is it possible?  
  "post-text" itemprop = "text"> 
 If there is a CPU load again there will be a load constraint for your code to work correctly, there are lots of architectures Who do such reinvention; See the table for some examples.  
 In this type of normal code, your code requires load constraints.  
 The x86 is not very specific, guarantees a very strong memory sequence in it for discussion.

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