system verilog - I am trying to code a 8-bit,4x1 multiplexer and I have seen some where that I can use a parameter to do so. Is there any other way to do it? -

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I'm trying an 8-bit, 4x1 multiplexer code and I have seen somewhere that I'm going to do this I can use the parameters. Is there any other way to do this? 

  module multiplier (a, b, c, d, select, y); Parameter size = 8; Input [7: 0] A, B, C, D; // Input Input [1: 0] Select; // 2-bit selection output [7: 0] y; // Select the output reg [7: 0]; Always @ (A or B or C or D or Selection) Case (Selection) // Select Case 0: y = a; 1: y = b; 2: y = c; 3: y = D; Default: y = 'bx; Endmodule   
 
 
 Since you have tagged it as SystemWirrol:  < Pre->  module multiplier # (parameter size = 8) (input [size -1: 0] select A, B, C, D, input [1: 0], output logic [size -1: 0] Y); Always_comb case (select) // Select the case 0: y = a; 1: y = b; 2: y = c; 3: y = D; Default: y = 'x; Endmodule

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