What does [`something] some_vector ; mean in verilog? -

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Assume that I have defined some macros, and then some other strings have been defined.
What does this mean when I like it? Does it just mean taking 2 LSBs from the wire? 

  Define 'AdEfien 32' * Here some code * Output ['adfine-1: 0] my_out_wire; // * More code here *   
 I can not find any explanation for this meaning.   
 
 
 syntax  define 'A_DEFINE 32'  a  A_DEFINE  Declared a macro. The macro is something you can use to make text replacements in your code.  
 Syntax  `ADefine`  means  A_DEFINE  extension of the macro is essentially assuming the value of  A_DEFINE  and Copying to the place where the macro has been expanded.  
 The preprocessor does this for you. In essence, you will end with:  
  // * Here are some code * Outputs [32-1: 0] my_out_wire; // * More code here *   
 Defines that your code needs to be a configurable element. In this way, if you have many hints that are in widespread form, then you define only if you need to change from 32 to 64, you can only define it and this is the same.  
 Also take a look at SystemVerilog  parameters . It can also be helpful.

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