Error count for two different patterns in verilog -

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I have created two types of data patterns and comparing their count as counting ..... when 2 The patterns are not equal, the error count should be high .... I have made the code with the test bench, but when I run the operation of the operation, the error number is only high on value 0 and not at value 1 ..... I hope this will be equal to 0 and 1. Please help me, because I'm new to verilog

Here is the code 

  'timecimal 1ns / 1ps module pattern (CLK, start, RST, code is clear here, Data_in1, data_in2, error); Input [1: 0] Data_In 1; Input [1: 0] Data_In 2; Input clique; Input started; Input rst; Clear input; Output [1: 0] error; Reg [1: 0] comp_out; Reg [1: 0] I = 0; Assign Error = comp_out; Always @ (posedge clk) comp_out = 0; If (rst) comp_out = 0; Otherwise start (i = 0; i & lt; 2; i = i + 1) starts at (data_in 1 [i]! = Data_in 2 [ii]) comp_out & lt; = Comp_out + 1; End end endmodule here is the test bench for codec 'timescale 1ns / 1ps module tb_pattern (); // inputs reg clk; Reg rst; Reg [1: 0] data_in1; Reg [1: 0] Data_In 2; Wire [1: 0] error; // output // wire [15: 0] count; // Testing Unit (UUT) Pattern Yt (//) (Calculate), .clc (CLK), start (start), .rst (rst), .ch (clear), .data 1 ( 1), .data_in2 (data_in2), .error (error)); Initial start clk = 1'b0; RST = 1'b 1; Repeat (4) # 10 clk = ~ clk; Rst = 1'b0; Forever # 10 clk = ~ clk; // Start the Start of a Clock Start / Begin inputs clk = 0; // rst = 1; Data_in1 = 2'b00; Data_in2 = 2'b01; # 100 data_in1 = 2'b11; Data_in2 = 2'b00; $ 100 end; After end / force delay // # 20 rst = 0; // # 25 rst = 1; When you move into the loop, you need to use the block assignment (); <= ), however, you should use the non-intercept assignment ( & lt; = ) while specifying the flop. When you need to use the loop to allocate the flop, it is best to split the combination and synchronous functionality into separate blocks.  
  ... reg [1: 0] comp_out, next_comb_out; Always @ * start: combs next_comp_out = 0; For (i = 0; i & lt; 2; i = i + 1) if it starts (data_in 1 [i]! = Data_in 2 [i]) next_comp_out = next_comp_out + 1; End end end always start @ (posedge clk): dff if (rst) comb_out start

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